Uart Data Ready Mikroc
- “Ready for PIC“ is one of MikroElektronika‘s compact prototyping boards for 28 and 40 pin PIC microcontrollers. The board comes with PIC16F887 microcontroller which is preprogrammed with an UART bootloader firmware and thus eliminates the need of an external programmer. The on-board USB-UART module allows the serial data transfer between the PIC and a PC using an USB cable.
- Uart Controlled DF Player Mikroc Code - 16F628A 1:29 PM 16F, Audio, PIC, Uart No comments The DFPlayer Mini MP3 Player is a small and low cost MP3 module with an simplified output directly to the speaker.
Chapter11: Serial InterfacingEmbeddedSystems - ShapeThe WorldJonathanValvanoand Ramesh YerraballiThischapter provides an introduction to serialinterfacing, which means we send one bit at time. Serial communicationis prevalent in both the computer industry in general and the embeddedindustry in specific. There are many serial protocols, but in thiscourse we will show you one of the first and simplest protocols thattransmit one bit at a time. We will show the theory and details of theuniversalasynchronousreceiver/transmitter (UART) and then use it as an example fordeveloping an I/Odriver.
I am using mikroC PRO for PIC and it makes the function code underlined by red, thus, making me not to compile it. Is it alright on USART if i'll try for example, when a character is send by uart for example 'A', then there would be certain command for it to light LED.
We will use busy-wait to synchronize the software with thehardware.LearningObjectives:. I/Osynchronization. Modelsof I/O devices (busy, done, off). Learnhow to program the UART. Builda distributed system by connecting two systems together. Learnhow to convert between numbers and ASCII stringsVideo 11.0.
Introduction to SerialCommunication11.1. I/O SynchronizationBefore we begin define serial communication, let's begin by introducingsome performance measures. As engineers and scientists we areconstantly making choices as we design new product or upgrade existingsystems. A performancemeasure is a quantitativemetric that the goodness of the system. The metrics and synchronizationalgorithms presented in this section will apply to all I/Ocommunication.Latencyisthe time between when the I/O device indicated service is required andthe timewhen service is initiated. Latency includes hardware delays in thedigitalhardware plus computer software delays. For an input device, softwarelatency(or software response time) is the time between new input data readyand thesoftware reading the data.
For an output device, latency is the delayfromoutput device idle and the software givingthe device new data tooutput. Inthis book, we will also have periodic events. For example, in our dataacquisition systems, we wish to invoke the analog to digital converter(ADC) ata fixed time interval.
In this way we can collect a sequence of digitalvaluesthat approximate the continuous analog signal. Software latency in thiscase isthe time between when the ADC conversion is supposed to be started, andwhen itis actually started.
The microcomputer-based control system alsoemploysperiodic software processing. Similar to the data acquisition system,thelatency in a control system is the time between when the controlsoftware issupposed to be run, and when it is actually run. A real-time systemis one that can guarantee a worst case latency.
In other words, thesoftwareresponse time is small and bounded. Furthermore, this bound is smallenough to satisfy overall specification of the system, such as no lostdata. Throughputorbandwidthisthe maximum data flow in bytes/second that can be processed by thesystem.Sometimes the bandwidth is limited by the I/O device, while other timesit islimited by computer software. Bandwidth can be reported as an overallaverageor a short-term maximum. Prioritydetermines the order ofservice whentwo or more requests are made simultaneously. Priority also determinesif ahigh-priority request should be allowed to suspend a low priorityrequest thatis currently being processed.
We may also wish to implement equalpriority, sothat no one device can monopolize the computer. In some computerliterature,the term 'soft-real-time' is used to describe a system that supportspriority.Thepurpose of our interface is to allow themicrocontrollerto interact with its external I/O device. One of the choices thedesigner must make is the algorithm for how the software synchronizeswith the hardware. There are five mechanisms tosynchronize the microcontroller with the I/O device.
Each mechanismsynchronizes the I/O data transfer to the busy to done transition. Themethodsare discussed in the following paragraphs.Figure11.1.
Synchronization MechanismsVideo 11.1. Device CommunicationrequiresSynchronizationBlindcycle isa method where the software simply waits a fixed amount of time andassumes theI/O will complete before that fixed delay has elapsed. For an inputdevice, thesoftware triggers (starts) the external input hardware, waits aspecified time,then reads data from device.
Blind cycle synchronization for an inputdevice is shown onthe left part of Figure 11.1. For anoutputdevice, shown on the left part of Figure 11.2, the software writes datato the output device, triggers(starts) thedevice, then waits a specified time. We call this method blind,becausethere is no status information about the I/O device reported to thesoftware. It is appropriate to use this method in situations where theI/Ospeed is short and predictable. We can ask the LCD to display an ASCIIcharacter, wait 37 µs, and then we are sure the operation iscomplete.
Thismethod works because the LCD speed is short and predictable. Anothergoodexample of blind-cycle synchronization is spinning a stepper motor. Ifwerepeat this 8-step sequence over and over 1) output a 0x05, 2) wait1ms, 3)output a 0x06, 4) wait 1ms, 5) output a 0x0A, 6) wait 1ms, 7)output a 0x09, 8)wait 1ms, the motor will spin at a constant speed.Figure11.2.
The output device sets a flag whenit hasfinished outputting the last data.InteractiveTool 11.1Usethe followingtool to see how blind-cycle synchronization works. You will need toenter a number between 1-10 to simulate the timing behavior of thedevice. Enter anamount oftime to wait (1-10):BusyWait is a software loop thatchecks theI/Ostatus waiting for the done state. For an input device, the softwarewaitsuntil the input device has new data, and then reads it from the inputdevice,see the middle parts of Figures 11.1 and 11.2.
For an output device,the softwarewritesdata, triggers the output device then waits until the device isfinished.Another approach to output device interfacing is for the software towait untilthe output device has finished the previous output, write data, andthentrigger the device. Busy-wait synchronization will be used insituations wherethe software system is relatively simple and real-time response is notimportant.The UART software in this chapter will use busy-wait synchronization.InteractiveTool 11.2Usethe followingtool to see how busy-wait synchronization works. You will press the'Ready' button to simulate the device being ready. Click to simulate I/Odevice becoming ready.An interruptuseshardware to cause special software execution. With an input device, thehardware will request an interrupt when input device has new data. Thesoftwareinterrupt service will read from the input device and save in globalRAM, seethe right parts of Figures 11.1 and 11.2. With an output device, thehardware willrequestan interrupt when the output device is idle.
The software interruptservicewill get data from a global structure, and then write to the device.Sometimeswe configure the hardware timer to request interrupts on a periodicbasis. Thesoftware interrupt service will perform a special function. A dataacquisitionsystem needs to read the ADC at a regular rate. Interruptsynchronization willbe used in situations where the system is fairly complex (e.g., a lotof I/Odevices) or when real-time response is important.
Interrupts will bepresented in Chapter 12.InteractiveTool 11.3Usethe followingtool to see how interrupt-based synchronization works. The foregroundthread and background thread (the Interrupt Service Routine or ISR)communicate using a buffer called a first in first out queue (FIFO). PeriodicPolling usesa clock interrupt to periodically check the I/O status. At the time oftheinterrupt the software will check the I/O status, performing actions asneeded.With an input device, a ready flag is set when the input device has newdata.At the next periodic interrupt after an input flag is set, the softwarewillread the data and save them in global RAM. With an output device, aready flagis set when the output device is idle.
At the next periodic interruptafter anoutput flag is set, the software will get data from a global structure,andwrite it. Periodic polling will be used in situations that requireinterrupts,but the I/O device does not support interrupt requests directly.DMA,or,directmemory access,is aninterfacing approach that transfers datadirectly to/from memory. With an input device, the hardware willrequest a DMAtransfer when the input device has new data. Without thesoftware’s knowledgeor permission the DMA controller will read data from the input deviceand saveit in memory. With an output device, the hardware will request a DMAtransferwhen the output device is idle.
The DMA controller will get data frommemory,and then write it to the device. Sometimes we configure the hardwaretimer torequest DMA transfers on a periodic basis. DMA can be used to implementahigh-speed data acquisition system.
DMA synchronization will be used insituations where high bandwidth and low latency are important. DMA willnot be covered in this introductory class. For details on how toimplement DMA on the LM4F120/TM4C123, see.One canthink of the hardware being in one of threestates.The idlestate is when the device is disabled or inactive. NoI/O occursin the idle state.
When active (not idle) the hardware toggles betweenthe busyand readystates. The interface includes a flagspecifying eitherbusy (0) or ready (1) status. Hardware-software synchronizationrevolves aroundthis flag: The hardware will set the flag whenthehardware component is complete. The software can read the flag todetermine ifthe device is busy or ready. The software can clear the flag,signifying thesoftware component is complete.
This flag serves as the hardwaretriggeringevent for an interrupt.For aninput device, a status flag is set when newinput datais available. The “busy to ready” state transitionwillcause a busy-wait loopto complete, see middle of Figure 11.1. Once the software recognizesthe inputdevice has new data, it will read the data and ask the input device tocreatemore data.
It is the busy toready state transition thatsignals to thesoftware that the hardware task is complete, and now software serviceisrequired. When the hardware is in the ready state the I/O transactioniscomplete. Often the simple process of reading the data will clear theflag andrequest another input.Theproblem with I/O devices is that they areusually muchslower than software execution. Therefore, we need synchronization,which isthe process of the hardware and software waiting for each other in amannersuch that data is properly transmitted. A way to visualize thissynchronizationis to draw a state versus time plot of the activities of the hardwareandsoftware.
For an input device, the software begins by waiting for newinput.When the input device is busy it is in the process of creating newinput. Whenthe input device is ready, new data is available. When the input devicemakesthe transition from busy to ready, it releases the software to goforward. In asimilar way, when the software accepts the input, it can release theinputdevice hardware.
The arrows in Figure 11.3 represent the synchronizingevents. Inthis example, the time for the software to read and process the data islessthan the time for the input device to create new input. This situationiscalledI/O bound, meaning thebandwidth is limited by the speed of theI/Ohardware.Figure11.3. The software must wait for the inputdevice tobe ready (I/O bound input interface).If theinput device were faster than the software,then thesoftware waiting time would be zero. This situation is called CPU bound(meaning the bandwidth is limited by the speed of the executingsoftware).Inreal systems the bandwidth depends on both the hardware and thesoftware.Another characteristic of real systems is the data can vary over time,likecar traffic arriving and leaving a road intersection. In other words,the sameI/Ochannel can sometimes be I/O bound, but at other times the channelcould be CPUbound.We canstore or buffer data in a firstin firstout(FIFO) queue, see Figure 11.4, while passing the data from one moduleto another. These modules may be input devices, output devices orsoftware.
Because the buffer separates the generation of data from theconsumption of data, it is very efficient, and hence it is prevalent inI/O communication. In particular, it can handle situations where thereis an increase or decrease in the rates at which data is produced orconsumed. Other names for this important interfacing mechanism include bounded buffer,producer-consumer,and bufferedI/O.
Data are entered intothe FIFO as they arrive; we callPuttostore data in the FIFO. Data are removed as they leave; we call Gettoremovedata from the FIFO. The FIFO maintains the order of the data, as itpassesthrough the buffer. We can think of a FIFO like a line at the postoffice.There is space in the lobby for a finite number of people to wait.
Ascustomersenter the post office they get in line at the end (put onto FIFO). Asthepostal worker services the customers, people at the front leave theline (getfrom the FIFO). It is bad situation (a serious error) if the waitingroombecomes full and there is no room for people to wait (full FIFO).However, ifthere are no customers waiting (empty FIFO) the postal worker sitsidle. Anempty FIFO may be inefficient, but it is not considered an error.Figure11.4. A FIFO queue can be used to passdata from aproducer to a consumer. At any given time there can be a variablenumber ofelements stored in the FIFO.
The order in which data are removed is thesame asthe order the data are entered.Thebusy-wait method is classified as unbufferedbecause thehardware and software must wait for each other during the transmissionof eachpiece of data. The interrupt solution (shown in the right part ofFigure 11.1)is classified as buffered, because the system allows the input deviceto run continuously,filling a FIFO with data as fast as it can. In the same way, thesoftware canempty the buffer whenever it is ready and whenever there is data in thebuffer.The buffering used in an interrupt interface may be a hardware FIFO, asoftwareFIFO, or both hardware and software FIFOs.
We will see the FIFO queueswillallow the I/O interface to operate during both situations: I/O boundand CPUbound.For anoutput device, a status flag is set when theoutput isidle and ready to accept more data. The “busy toready”state transition causesa busy-wait loop to complete, see the middle part of Figure 11.2.
Oncethesoftware recognizes the output is idle, it gives the output deviceanotherpiece of data to output. It will be important to make sure the softwareclearsthe flag each time new output is started. Figure11.5 contains a state versus time plot oftheactivities of the output device hardware and software. For an outputdevice,the software begins by generating data then sending it to the outputdevice.When the output device is busy it is processing the data. Normally whenthesoftware writes data to an output port, that only starts the outputprocess.
Thetime it takes an output device to process data is usually longer thanthesoftware execution time. When the output device is done, it is readyfor newdata. When the output device makes the transition from busy to ready,itreleases the software to go forward.
In a similar way, when thesoftware writesdata to the output, it releases the output device hardware. The outputinterface illustrated in Figure 11.5 is also I/O bound because the timefor theoutput device to process data is longer than the time for the softwaretogenerate and write it. Again, I/O bound means the bandwidth is limitedby thespeed of the I/O hardware.Figure11.5. The software must wait for theoutput deviceto finish the previous operation (I/O bound).Thebusy-wait solution for this output interface isalsounbuffered, because when the hardware is done, it will wait for thesoftwareand after the software generates data, it waits for the hardware. Onthe otherhand, the interrupt solution (shown as the right part of Figure 11.2)isbuffered, because the system allows the software to run continuously,filling aFIFO as fast as it wishes. In the same way, the hardware can empty thebufferwhenever it is ready and whenever there is data in the FIFO. Again,FIFO queuesallow the I/O interface to operate during both situations: I/O boundand CPUbound.On somesystems an interrupt will be generated on ahardwarefailure.
Examples include power failure, temperature too high, memoryfailure,and mechanical tampering of secure systems. Usually, these events areextremelyimportant and require immediate attention. The Cortex™-Mprocessor will executespecial software ( fault)when it tries to execute an illegal instruction, access an illegalmemorylocation, or attempt an illegal I/O operation. Universal AsynchronousReceiver Transmitter (UART)Video 12.2a.
UART Background andLaunchpad SupportVideo 12.2b. UART OperationIn this sectionwe willdevelop a simple device driver using the Universal AsynchronousReceiver/Transmitter (UART).
This serial port allows themicrocontroller to communicate with devices suchas other computers, printers, input sensors, and LCDs. Serialtransmission involves sending one bit at a time, such that thedata is spread out over time. Thetotal number of bits transmitted per second is called the baudrate.The reciprocal of the baud rate is the bittime, which is thetime to sendone bit. Most microcontrollers have at least one UART.
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TheLM4F120/TM4C123 has 8 UARTs. Beforediscussing thedetailed operation on the TM4C, we will begin with general featurescommon toall devices. Each UART will have a baud rate control register, which weuse toselect the transmission rate.
Each device is capable of creating itsown serialclock with a transmission frequency approximately equal to the serialclock inthe computer with which it is communicating. A frame isthe smallest complete unit of serial transmission. Figure 11.6 plotsthe signalversus time on a serial port, showing a single frame, which includes a startbit (which is 0), 8bits of data (least significant bitfirst), and a stopbit (which is 1). There isalways only one start bit, but theStellaris ®UARTs allow usto select the 5 to 8 data bits and 1 or 2 stop bits.
The UART can addeven,odd, or no parity bit. However, we will employ the typical protocol of1 startbit, 8 data bits, no parity, and 1 stop bit.
This protocol is used forbothtransmitting and receiving. The information rate, or bandwidth,is defined as the amount of data or useful information transmitted persecond.From Figure 11.6, we see that 10 bits are sent for every byte of usualdata.Therefore, the bandwidth of the serial channel (in bytes/second) is thebaudrate (in bits/sec) divided by 10.Figure11.6. A serial data frame with 8-bit data,1 startbit, 1 stop bit, and no parity bit.CommonError: If you change the busclockfrequencywithout changing the baud rate register, the UART will operate at anincorrectbaud rate.Checkpoint 11.1: Assuming theprotocol drawn in Figure 11.6 and a baud rate of 1000 bits/sec, what isthebandwidth in bytes/sec?Table11.1 shows the three most commonly usedRS232 signals. The EIA-574 standard uses RS232voltage levelsand a DB9 connector thathas only 9 pins.
The most commonly used signals of the full RS232standard areavailable with the EIA-574 protocols. Only TxD,RxD,and SGare required to implement a simple bidirectional serial channel, thusthe othersignals are not shown (Figure 11.7). We define the dataterminalequipment (DTE) as thecomputer or a terminal and the datacommunication equipment (DCE)as the modem or printer.DB9PinEIA-574NameSignalDescriptionTrueDTEDCE3103TxDTransmitData-5.5Voutin2104RxDReceiveData-5.5Vinout5102SGSignalGroundTable11.1. The commonly-used signals on theEIA-574protocol.Figure11.7.
Hardwareinterfaceimplementing an asynchronous RS232 channel. The TM4C123 has eight UARTports.Observation:The LaunchPad sends UART0channelthrough the USB cable, so the circuit shown in Figure 11.7 will not beneeded.On the PC side of the cable, the serial channel becomes a virtual COMport.RS232is a non-return-to-zero (NRZ) protocolwith truesignified as a voltage between -5 and ‑15 V. False is signified by avoltage between +5 and +15 V. A MAX3232 converter chip is usedtotranslatebetween the +5.5/-5.5 V RS232 levels and the 0/+3.3 V digital levels.Thecapacitors in this circuit are important, because they form a chargepump usedto create the ±5.5 voltages from the +3.3 V supply. TheRS232timing isgenerated automatically by the UART. During transmission,the MAX3232translates a digital high on microcontroller side to -5.5V on theRS232/EIA‑574cable, and a digital low is translated to +5.5V. During receiving,the MAX3232translates negative voltages on RS232/EIA‑574 cable to a digital highonthe microcontroller side, and a positive voltage is translated to adigitallow.
The computer is classified as DTE, so its serial output is pin 3in theEIA‑574 cable, and its serial input is pin 2 in the EIA‑574 cable.When connecting a DTE to another DTE, we use a cable with pins 2 and 3crossed.I.e., pin 2 on one DTE is connected to pin 3 on the other DTE and pin 3on oneDTE is connected to pin 2 on the other DTE. When connecting a DTE to aDCE,then the cable passes the signals straight across. In all situations,thegrounds are connected together using the SG wire in the cable. Thischannel isclassified as full-duplex,because transmission can occur inbothdirections simultaneously. AsynchronousCommunicationWewill begin with transmission, because it issimple.
Thetransmitter portion of the UART includes a data output pin, withdigital logiclevels as drawn in the following interactive tool. The transmitter hasa 16-element FIFOand a10-bit shift register, which cannot be directly accessed by theprogrammer.
The FIFO and shift register in the transmitter areseparate fromthe FIFO and shift register associated with the receiver. In otherwords each UART has a receiver and a transmitter, but the interactivetool just shows the transmitter on one microcontroller and the receiveron the other. To outputdata using theUART, the transmitter software will first check to make sure thetransmit FIFO isnot full(it will wait if TXFFis 1) and then write to the transmit dataregister(e.g., UART0DRR).The bits are shifted out in this order: start, b 0,b 1,b 2,b 3,b 4,b 5,b 6,b 7,and then stop, where b 0 is the LSB and b 7isthe MSB. The transmitdataregister is write only, which means the software can write to it (tostart anew transmission) but cannot read from it.
Even though the transmitdataregister is at the same address as the receive data register, thetransmit andreceive data registers are two separate registers. The transmissionsoftware can write to its data register if its TXFF (transmit FIFOfull) flag is zero. TXFF equal to zero means the FIFO is not full andhas room. The receiving software can read from its dataregister if its RXFE(receive FIFO empty) flag is zero.
RXFE equal to zero means the FIFO isnot empty and has some data. While playing the followinginteractive tool, watch the behavior of the TXFF and RXFE flags.InteractiveTool 11.4Usethe followingtool to watch the steps involved in Serial Communication of a simpletwo-byte message. Click Start/next over and over to single step theprocess, and click Run to run the entire sequence.Click Start to Send 'H' to the direction register. Whena new byte is written to UART0DRR,it is putinto the transmit FIFO. Byte bybyte, the UART gets data from the FIFO and loads them into the 10-bittransmitshift register.
The 10-bit shift register includes a start bit, 8 databits,and 1 stop bit. Then, the frame is shifted out one bit at a time at aratespecified by the baud rate register. If there are already data in theFIFO orin the shift register when the UART0DRRis written, the new frame will wait until the previous frames have beentransmitted, before it too is transmitted. The FIFO guarantees the dataaretransmitted in the order they were written. The serial port hardware isactually controlled by a clock that is 16 times faster than the baudrate,referred to in the datasheet as Baud16.When the data are beingshiftedout, the digital hardware in the UART counts 16 times in betweenchanges to theU0Txoutput line.Thesoftware can actually write 16 bytes to the UART0DRR,and thehardware willsend them all one at a time in the proper order.
This FIFO reduces thesoftwareresponse time requirements of the operating system to servicethe serial port hardware. Unfortunately, it does complicate thehardware/software timing. At 9600 bits/sec, it takes 1.04 ms to send aframe.Therefore, there will be a delay ranging from 1.04 and 16.7 ms betweenwriting tothe data register and the completion of the data transmission. Thisdelaydepends on how much data are already in the FIFO at the time thesoftwarewrites to UART0DRR.Receivingdata frames is a little trickier thantransmission because we have to synchronize the receive shift registerwith theincoming data. The receiver portion of the UART includes a U0Rxdatainput pin with digital logic levels. At the input of themicrocontroller, trueis 3.3V and false is 0V. There is also a 16-element FIFO and a 10-bitshiftregister, which cannot be directly accessed by the programmer (shown onthe right side of the interactive tool).The receive shift register is 10 bits wide, but the FIFO is 12 bits, 8bits of data and 4 error flags.
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Again the receive shift register andreceive FIFO are separate fromthose inthe transmitter. The receive data register, UART0DRR,is read only, which means write operations to this address have noeffect onthis register (recall write operations activate the transmitter). Thereceiverobviously cannot start a transmission, but it recognizes a new frame byitsstart bit. The bits are shifted in using the same order as thetransmittershifted them out: start, b 0,b 1,b 2,b 3,b 4,b 5,b 6,b 7,and then stop.Thereare six status bits generated by receiveractivity.The Receive FIFO empty flag, RXFE,is clear when new input dataare inthe receive FIFO. When the software reads fromUART0DRR,data are removed from the FIFO. When the FIFObecomesempty, the RXFEflag will be set, meaning there are no moreinput data.There are other flags associated with the receiver. There is a ReceiveFIFOfull flag RXFF,which is set when the FIFO is full.
There arefourstatus bits associated with each byte of data. For this reason, thereceiveFIFO is 12 bits wide. The overrun error, OE,is set when inputdata arelost because the FIFO is full and more input frames are arriving at thereceiver.An overrun error is caused when the receiver interface latencyistoo large.The break error, BE,is set when the input is held low for morethan aframe. Parity is a mechanism to send one extra bit so the receiver candetect if there were any errors in transmission. With even parity thenumber of 1's in the data plus parity will be an even number. The PEbit is set on a parity error.
Because the errorrate is solow, most systems do not implement parity. We will not use parity inthis class. The framing error,FE,is set when the stop bit is incorrect.
Framing errors areprobablycaused by a mismatch in baud rate.Thereceiver waits for the 1 to 0 edgesignifying a startbit, then shifts in 10 bits of data one at a time from the U0Rxline.The internal clock is 16 times faster than the baud rate. After the 1to 0edge, the receiver waits 8 internal clocks and samples the start bit.16 internalclocks later it samples b 0.Every 16 internal clocksit samplesanother bit until it reaches the stop bit. The UART needs an internalclockfaster than the baud rate so it can wait the half a bit time betweenthe 1 to 0edge beginning the start bit and the middle of the bit window neededforsampling. The start and stop bits are removed (checked for framingerrors), the 8 bits of data and 4 bits of status are put into thereceive FIFO. The hardwareFIFO implements buffering so data is safely stored in the receiverhardware ifthe software is performing other tasks while data is arriving.Observation:If the receiving UART devicehas a baudrate mismatch of more than 5%, then a framing error can occur when thestop bitis incorrectly captured.Anoverrun occurs when there are 16 elements inthereceive FIFO, and a 17 thframe comes into the receiver. Inorder toavoid overrun, we can design a real-time system, i.e., one with amaximumlatency. The latency of a UART receiver is the delay betweenthetime when newdata arrives in the receiver ( RXFE=0)and the time the softwarereadsthe data register.
If the latency is always less than 160 bit times,thenoverrun will never occur.Observation:With a serial port that has ashiftregister and one data register (no FIFO buffering), the latencyrequirement ofthe input interface is the time it takes to transmit one data frame. 11.2.2.TM4C UART DetailsNextwe will overview the specific UARTfunctions on the TM4Cmicrocontroller. This section is intended to supplement rather thanreplace theTexas Instruments manuals. When designing systems with any I/O module,you mustalso refer to the reference manual of your specific microcontroller.
Itis alsogood design practice to review the errata for your microcontroller tosee ifany quirks (mistakes) exist in your microcontroller that might apply tothesystem you are designing.StellarisTM4C microcontrollers have eightUARTs. Thespecific port pins used to implement the UARTs vary from one chip tothe next.To find which pins your microcontroller uses, you will need to consultitsdatasheet. Table 11.2 shows some of the registers for the UART0 andUART1. Forthe other UARTs, the register names will replace the 0 with a 1–7.
For theexact register addresses, you should include the appropriate headerfile (e.g.,tm4c123gh6pm.h).To activate a UART you will need to turn on theUARTclock in the RCGC1register. You should also turn on the clockfor thedigital port in the RCGC2register. You need to enable thetransmit andreceive pins as digital signals. The alternative function for thesepins mustalso be selected. In particular we set bits in both the AFSEL and PCTLregisters.TheOE, BE, PE, and FE are error flagsassociated with thereceiver. You can see these flags in two places: associated with eachdata bytein UART0DRRor as aseparate error register in UART0RSRR.The overrun error ( OE)is set if data has been lost because theinputdriver latency is too long. BEis a break error, meaning theother devicehas sent a break.
PEis a parity error (however, we will not beusingparity). Ea cricket 2002 torrent. The framing error ( FE)will get set if the baud ratesdo notmatch. The software can clear these four error flags by writing anyvalue to UART0RSRR.Thestatus of the two FIFOs can be seen in the UART0FRRregister.The BUSYflag is set while the transmitter still has unsent bits, even if thetransmitter is disabled. It will become zero when the transmit FIFO isemptyand the last stop bit has been sent. If you implement busy-wait outputby firstoutputting then waiting for BUSYto become 0 (right flowchartof Figure 11.10),then the routine will write new data and return after that particulardata hasbeen completely transmitted.The UART0CTLRcontrol register contains the bits that turn on the UART. TXE isthe Transmitter Enable bit, and RXE isthe Receiver Enablebit. We set TXE,RXE,and UARTENequal to 1 in order to activate the UARTdevice.However, we should clear UARTENduring the initializationsequence.87–0Name$4000.C000OEBEPEFEDATAUART0DRR31–.C004OEBEPEFEUART0RSRR–0$4000.C018TXFERXFFTXFFRXFEBUSYUART0FRR31–1615–0$4000.C024DIVINTUART0IBRDR31–65–0$4000.C028DIVFRACUART0FBRDR76– 5.C02CSPSWPENFENSTP2EPSPENBRKUART0LCRHR31–1$4000.C030RXETXELBESIRLPSIRENUARTENUART0CTLR87–0$4000.D000OE.